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IC80LV52 IC80LV32
IC80LV52 IC80LV32
CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER
FEATURES
* * * * * * * * * 80C51 based architecture 8K x 8 ROM (IC80LV52 only) 256 x 8 RAM Three 16-bit Timer/Counters Full duplex serial channel Boolean processor Four 8-bit I/O ports, 32 I/O lines Memory addressing capability - 64K ROM and 64K RAM Program memory lock - Encrypted verify (32 bytes) - Lock bits (2) Power save modes: - Idle and power-down Eight interrupt sources Most instructions execute in 0.5 s CMOS and TTL compatible Maximum speed: 24 MHz @ Vcc = 3.3V Packages available: - 40-pin DIP - 44-pin PLCC - 44-pin PQFP
GENERAL DESCRIPTION
The ICSI IC80LV52 and IC80LV32 are high-performance microcontrollers fabricated using high-density CMOS technology. The CMOS IC80LV52/32 is functionally compatible with the industry standard 8052/32 microcontrollers. The IC80LV52/32 is designed with 8K x 8 ROM (IC80LV52 only); 256 x 8 RAM; 32 programmable I/O lines; a serial I/O port for either multiprocessor communications, I/O expansion or full duplex UART; three 16-bit timer/counters; an eight-source, two-priority-level, nested interrupt structure; and an on-chip oscillator and clock circuit. The IC80LV52/32 can be expanded using standard TTL compatible memory.
* * * * * *
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
Figure 1. IC80LV52/32 Pin Configuration: 40-pin DIP
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
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IC80LV52 IC80LV32
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
INDEX P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 17
6
5
4
3
2
1
44
43
42
41
P0.3/AD3
P1.0/T2
P1.4
P1.3
P1.2
VCC
NC
40 39 38 37 36 35 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NC ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
TOP VIEW
34 33 32 31 30 29
18
WR/P3.6
19
RD/P3.7
20
XTAL2
21
XTAL1
22
GND
23
NC
24
A8/P2.0
25
A9/P2.1
26
A10/P2.2
27
A11/P2.3
28
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Figure 2. IC80LV52/32 Pin Configuration: 44-pin PLCC
2
IC80LV52 IC80LV32
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
P1.0/T2
P1.4
P1.3
P1.2
44 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 1 2 3 4 5 6 7 8 9 10 11 12
43
42
41
40
39
VCC
NC
38
37
36
35
P0.3/AD3
34 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NC ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
13
14
15
16
17
18
19
20
21
22
WR/P3.6
XTAL2
XTAL1
RD/P3.7
GND
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
Figure 3. IC80LV52/32 Pin Configuration: 44-pin PQFP
A12/P2.4
NC
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IC80LV52 IC80LV32
P2.0-P2.7
P0.0-P0.7
VCC
P2 DRIVERS
P0 DRIVERS
GND ADDRESS DECODER & 256 BYTES RAM ADDRESS 2 LOCK BITS DECODER & & 32 BYTES 8K ROM ENCRYPTION
RAM ADDR REGISTER
P2 LATCH
P0 LATCH
B REGISTER
STACK POINT
ACC
PROGRAM ADDRESS REGISTER
PCON SCON T2CON TH0 TL1 TH2 RCAP2L SBUF
TMOD TCON TL0 TH1 TL2 RCAP2H IE IP
TMP2
TMP1
PROGRAM COUNTER
INTERRUPT SERIAL PORT AND TIMER BLOCK
ALU
PC INCREMENTER
PSW BUFFER
PSEN ALE RST EA TIMING AND CONTROL
INSTRUCTION REGISTER
DPTR
P3 LATCH OSCILLATOR XTAL1 XTAL2 P3 DRIVERS
P1 LATCH
P1 DRIVERS
P3.0-P3.7
P1.0-P1.7
Figure 4. IC80LV52/32 Block Diagram
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Table 1. Detailed Pin Description Symbol ALE PDIP 30 PLCC 33 PQFP 27 I/O I/O Name and Function Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. External Access enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 1FFFH. Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). The Port 1 output buffers can sink/source four TTL inputs. Port 1 also receives the low-order address byte during ROM verification. 1 2 P2.0-P2.7 21-28 2 3 24-31 40 41 18-25 I I I/O T2(P1.0): Timer/Counter 2 external count input. T2EX(P1.1): Timer/Counter 2 trigger input. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that used 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order bits and some control signals during ROM verification.
EA
31
35
29
I
P0.0-P0.7
39-32
43-36
37-30
I/O
P1.0-P1.7
1-8
2-9
40-44 1-3
I/O
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IC80LV52 IC80LV32
Table 1. Detailed Pin Description (continued) Symbol P3.0-P3.7 PDIP 10-17 PLCC 11, 13-19 PQFP 5, 7-13 I/O I/O Name and Function Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). Port 3 also serves the special features of the IC80LV52/32, as listed below: 10 11 12 13 14 15 16 17 PSEN 29 11 13 14 15 16 17 18 19 32 5 7 8 9 10 11 12 13 26 I O I I I I O O O RxD (P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt 0. INT1 (P3.3): External interrupt 1. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6): External data memory write strobe. RD (P3.7): External data memory read strobe. Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal MOS resistor to GND permits a power-on reset using only an external capacitor connected to Vcc. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. Ground: 0V reference. Power Supply: This is the power supply voltage for operation.
RST
9
10
4
I
XTAL 1 XTAL 2 GND Vcc
19 18 20 40
21 20 22 44
15 14 16 38
I O I I
OPERATING DESCRIPTION
The detail description of the IC80LV52/32 included in this description are: * Memory Map and Registers * Timer/Counters * Serial Interface * Interrupt System * Other Information The detail information desription of the IC80LV52/32 refer to IC80C52/32 data sheet
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OTHER INFORMATION Reset
The reset input is the RST pin, which is the input to a Schmitt Trigger. A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. The CPU responds by generating an internal reset, with the timing shown in Figure 6. The external reset signal is asynchronous to the internal clock. The RST pin is sampled during State 5 Phase 2 of every machine cycle. The port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin; that is, for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin. The internal reset algorithm writes 0s to all the SFRs except the port latches, the Stack Pointer, and SBUF. The port latches are initialized to FFH, the Stack Pointer to 07H, and SBUF is indeterminate. Table 2 lists the SFRs and their reset values. Then internal RAM is not affected by reset. On power-up the RAM content is indeterminate. Table 2. Reset Values of the SFR's SFR Name PC ACC B PSW SP DPTR P0-P3 IP IE TMOD TCON T2CON TH0 TL0 TH1 TL1 TH2 TL2 RCAP2H RCAP2L SCON SBUF PCON Reset Value 0000H 00H 00H 00H 07H 0000H FFH XX000000B 0X000000B 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Indeterminate 0XXX0000B
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IC80LV52 IC80LV32
Power-on Reset
An automatic reset can be obtained when VCC goes through a 10F capacitor and GND through an 8.2K resistor, providing the VCC rise time does not exceed 1 msec and the oscillator start-up time does not exceed 10 msec. This power-on reset circuit is shown in Figure 5. The CMOS devices do not require the 8.2K pulldown resistor, although its presence does no harm. When power is turned on, the circuit holds the RST pin high for an amount of time that depends on the value of the capacitor and the rate at which it charges. To ensure a good reset, the RST pin must be high long enough to allow the oscillator time to start-up (normally a few msec) plus two machine cycles. Note that the port pins will be in a random state until the oscillator has start and the internal reset algorithm has written 1s to them. With this circuit, reducing VCC quickly to 0 causes the RST pin voltage to momentarily fall below 0V. However, this voltage is internally limited, and will not harm the device. Vcc 10 F + -
Vcc IC80LV52/32 RST
8.2K GND
Figure 5. Power-On Reset Circuit
12 OSC. PERIODS
S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
RST
INTERNAL RESET SIGNAL SAMPLE RST SAMPLE RST
ALE PSEN P0
INST ADDR INST ADDR INST ADDR INST ADDR INST ADDR
11 OSC. PERIODS
19 OSC. PERIODS
Figure 6. Reset Timing
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Power-Saving Modes of Operation
The IC80LV52/32 has two power-reducing modes. Idle and Power-down. The input through which backup power is supplied during these operations is Vcc. Figure 7 shows the internal circuitry which implements these features. In the Idle mode (IDL = 1), the oscillator continues to run and the Interrupt, Serial Port, and Timer blocks continue to be clocked, but the clock signal is gated off to the CPU. In Power-down (PD = 1), the oscillator is frozen. The Idle and Power-down modes are activated by setting bits in Special Function Register PCON. Idle Mode An instruction that sets PCON.0 is the last instruction executed before the Idle mode begins. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the Interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into Idle. The flag bits GF0 and GF1 can be used to indicate whether an interrupt occurred during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset must be held active for only two machine cycles (24 oscillator periods) to complete the reset. The signal at the RST pin clears the IDL bit directly and asynchronously. At this time, the CPU resumes program execution from where it left off; that is, at the instruction following the one that invoked the Idle Mode. As shown in Figure 22, two or three machine cycles of program execution may take place before the internal reset algorithm takes control. On-chip hardware inhibits access to the internal RAM during his time, but access to the port pins is not inhibited. To eliminate the possibility of unexpected outputs at the port pins, the instruction following the one that invokes Idle should not write to a port pin or to external data RAM.
XTAL 1 OSC
XTAL 2 INTERRUPT, SERIAL PORT, TIMER BLOCKS CPU
CLOCK GEN PD
IDL
Figure 7. Idle and Power-Down Hardware
Power-down Mode An instruction that sets PCON.1 is the last instruction executed before Power-down mode begins. In the Powerdown mode, the on-chip oscillator stops. With the clock frozen, all functions are stopped, but the on-chip RAM and Special function Registers are held. The port pins output the values held by their respective SFRs. ALE and PSEN output lows. In the Power-down mode of operation, Vcc can be reduced to as low as 2V. However, Vcc must not be reduced before the Power-down mode is invoked, and Vcc must be restored to its normal operating level before the Power-down mode is terminated. The reset that terminates Power-down also frees the oscillator. The reset should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (normally less than 10 msec). The only exit from power-down is a hardware reset. Reset redefines all the SFRs but does not change the on-chip RAM.
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IC80LV52 IC80LV32
Table 3. Status of the External Pins During Idle and Power-down Modes. Mode Idle Idle Power-down Power-down Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
On-Chip Oscillators
The on-chip oscillator circuitry of the IC80LV52/32 is a single stage linear inverter, intended for use as a crystalcontrolled, positive reactance oscillator (Figure 8). In this application the crystal is operated in its fundamental response mode as an inductive reactance in parallel resonance with capacitance external to the crystal (Figure 8). Examples of how to drive the clock with external oscillator are shown in Figure 9.
The crystal specifications and capacitance values (C1 and C2 in Figure 8) are not critical. 20 pF to 30 pF can be used in these positions at a12 MHz to 24 MHz frequency with good quality crystals. A ceramic resonator can be used in place of the crystal in cost-sensitive applications. When a ceramic resonator is used, C1 and C2 are normally selected to be of somewhat higher values. The manufacturer of the ceramic resonator should be consulted for recommendation on the values of these capacitors.
C2 XTAL2
NC XTAL2
C1 XTAL1
EXTERNAL OSCILLATOR SIGNAL
XTAL1
GND
GND
Figure 8. Oscillator Connections
Figure 9. External Clock Drive Configuration
Table 4. Recommended Value for C1, C2, R Frequency Range 4 MHz-24 MHz 30 MHz-40 MHz 20 pF-30 pF - 20 pF-30 pF - Not Apply -
C1 C2 R
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ROM Verification
The address of the program memory location to be read is applied to Port 1 and pins P2.4-P2.0. The other pins should be held at the "Verify" level are indicated in Figure 10. The contents of the addressed locations exits on Port 0. External pullups are required on Port 0 for this operation. Figure 10 shows the setup to verify the program memory.
+ 3.3V .
A7-A0
P1
Vcc
A12-A8 1 1 1 0 0 0
P2.4-P2.0 RST EA ALE PSEN P2.7 P2.6 XTAL1 P0
10K x 8
PGM DATA
4-6 MHz XTAL2 GND
Figure 10. ROM Verification
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IC80LV52 IC80LV32
ROM Lock System
The program lock system, when programmed, protects the ROM code against software piracy. The IC80LV52/32 has a two-level program lock system (see Table 5) and a 32-byte encryption table. No matter what lock bit is, the user submits the encryption table with his or her code in verify ROM mode. Both the lock-bit and encryption array programmed by the factory.
Encryption Array
Within the ROM array are 32 bytes of Encryption Array that are initially unprogrammed (all 1's). Every time that a byte is addressed during verify, five address lines are used to select a byte of the Encryption Array.This byte is then exclusive-NOR'ed (XNOR) with the code byte, creating an Encryption verify byte. The algorithm, with the array in the unprogrammed state (all 1's), will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a code byte has the value 0FFH, verifying the byte will produce the encryption byte value. If a large block (> 32 bytes) of code is left unprogrammed, a verification routine will display the contents of the encryption array. For this reason, all unused code bytes should be programmed with some value other than 0FFH, and not all of them the same value.
Table 5. Program Lock Bits 1 2 LB1 U P LB2 U U Protection Type No Program Lock Features enabled. (Code verify will still be encrypted by the Encryption Array if Programmed) MOVC instructions executed from external program memory are diabled form fetching code bytes from internal memory, EA is sampled and latched on Reset. Same as 2, also ROM verify is disabled.
3
P
P
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND(2) Temperature Under Bias(3) Storage Temperature Power Dissipation Value -2.0 to +7.0 0 to +70 -65 to +125 1.5 Unit V C C W
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may overshoot to Vcc + 2.0V for periods less than 20 ns. 3. Operating temperature is for commercial products only defined by this specification.
OPERATING RANGE(1)
Range Commercial Ambient Temperature 0C to +70C VCC 3.3V 10% Oscillator Frequency 3.5 to 24 MHz
Note: 1. Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC CHARACTERISTICS
(TA = 0C to 70C; Vcc = 3.3V 10%; GND = 0V) Symbol VIL VIL1 VIH VIH1 VSCH+ VSCH- Vol(1) VOL1
(1)
Parameter Input low voltage (All except EA) Input low voltage (EA) Input high voltage (All except XTAL 1, RST) Input high voltage (XTAL 1) RST positive schmitt-trigger threshold voltage RST negative schmitt-trigger threshold voltage Output low voltage (Ports 1, 2, 3) Output low voltage (Port 0, ALE, PSEN) Output high voltage (Ports 1, 2, 3, ALE, PSEN) Output high voltage (Port 0, ALE, PSEN) Input leakage current (Port 0) Logical 1-to-0 transition current (Ports 1, 2, 3) RST pulldown resister
Test conditions
Min -0.5 -0.5 0.2Vcc + 0.9 0.7Vcc 0.7Vcc 0
Max 0.2Vcc + 0.1 0.2Vcc + 0.1 Vcc + 0.5 Vcc + 0.5 Vcc + 0.5 0.3Vcc 0.45 0.45 -- -- -50 5 -450 450
Unit V V V V V V V V V V A A A K
IOL = 1.6 mA IOL = 3.2 mA IOH = -20 A IOH = -800 A
-- -- Vcc-0.9 Vcc-0.9 -- -5 -- 150
VOH VOH1 IIL ILI ITL RRST
Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V 0.45V < VIN < Vcc VIN = 2.0V
Note:
1. Under steady state (non-transient) conditions, Iol must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink greater than the listed test conditions.
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POWER SUPPLY CHARACTERISTICS
Symbol Icc Parameter Power supply current Active mode Idle mode Power-down mode
Note: 1. See Figures 11, 12, 13, and 14 for Icc test conditiions.
(1)
Test conditions Vcc = 3.3V 12 MHz 24 MHz 12 MHz 24 MHz VCC = 3.3V
Min -- -- -- -- --
Max 15 24 4 8 50
Unit mA mA mA mA A
Vcc Vcc RST Vcc Vcc P0
P0
Vcc Icc RST Vcc Vcc
Icc
NC CLOCK SIGNAL
XTAL2 XTAL1 GND
NC CLOCK SIGNAL
XTAL2 XTAL1 GND
EA
EA
Figure 11. Active Mode
Vcc Icc RST Vcc Vcc P0
Figure 12. Idle Mode
NC
XTAL2 XTAL1 GND
EA
Figure 13. Power-down Mode
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IC80LV52 IC80LV32
tCLCX
Vcc -- 0.5V 0.45V
0.7Vcc 0.2Vcc -- 0.1
tCHCX
tCHCL tCLCL
tCLCH
Figure 14. Clock Signal Waveform for Icc Tests in Active and Idle Modes. (tCLCH=tCHCL=5 ns)
AC CHARACTERISTICS
(TA = 0C to 70C; Vcc = 3.3V 10%; GND = 0V; Cl for Port 0, ALE and PSEN Outputs = 100 pF; Cl for other outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
12 MHz Clock Min Max -- -- 152 -- 68 -- 73 -- -- 313 73 -- 235 -- -- 230 0 -- -- 78 -- 397 -- 10 480 -- 480 -- -- 323 0 -- -- 162 -- 573 -- 656 230 270 313 -- 68 -- 73 -- -- 0 68 98 24 MHz Clock Min Max ---- 68 -- 26 -- 31 -- -- 147 31 -- 110 -- -- 105 0 -- -- 37 -- 188 -- 10 230 -- 230 -- -- 157 0 -- -- 78 -- 282 -- 323 105 145 146 -- 26 -- 31 -- -- 0 26 57 Variable Oscillator (3.5-24 MHz) Min Max 3.5 24 2tCLCL-15 -- tCLCL-15 -- tCLCL-10 -- -- 4tCLCL-20 tCLCL-10 -- 3tCLCL-15 -- -- 3tCLCL-20 0 -- -- tCLCL-5 -- 5tCLCL-20 -- 10 6tCLCL-20 -- 6tCLCL-20 -- -- 4tCLCL-10 0 -- -- 2tCLCL-5 -- 7tCLCL-10 -- 8tCLCL-10 3tCLCL-20 3tCLCL+20 4tCLCL-20 -- tCLCL-15 -- tCLCL-10 -- -- 0 tCLCL-15 tCLCL+15
Symbol 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH
Parameter Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instr in ALE low to PSEN low PSEN pulse width PSEN low to valid instr in Input instr hold after PSEN Input instr float after PSEN Address to valid instr in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address to RD or WR low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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EXTERNAL MEMORY CHARACTERISTICS
(CONTINUED) 12 MHz Clock Min Max 990 1010 823 -- 157 0 -- -- -- 833 24 MHz Clock Min Max 290 310 240 -- 40 0 -- -- -- 250 Variable Oscillator (3.5-24 MHz) Min Max 12tCLCL-10 12tCLCL+10 10tCLCL-10 -- 2tCLCL-10 0 -- -- -- 10tCLCL
Symbol tXLXL tQVXH tXHQX tXHDX tXHDV
Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
Unit ns ns ns ns ns
EXTERNAL CLOCK DRIVE
Symbol 1/tCLCL tCHCX tCLCX tCLCH tCHCL wParameter Oscillator Frequency High time Low time Rise time Fall time Min 3.5 10 10 -- -- Max 40 -- -- 10 10 Unit MHz ns ns ns ns
ROM VERIFICATION CHARACTERISTICS
Symbol 1/tCLCL tAVQV tELQV tEHQZ Parameter Oscillator Frequency Address to data valid ENABLE low to data valid Data float after ENABLE Min 4 -- -- 0 Max 6 48tCLCL 48tCLCL 48tCLCL Unit MHz
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TIMING WAVEFORMS
tLHLL
ALE
tLLPL tAVLL tPLPH tPLIV tPLAZ tPXIZ
A7-A0
PSEN
tLLAX tPXIX
INSTR IN
PORT 0
A7-A0
tLLIV tAVIV
PORT 2
A15-A8
A15-A8
Figure 15. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL tAVLL tRLAZ tLLAX
tRLRH tRHDZ tRHDX
DATA IN A7-A0 FROM PCL INSTR IN
RD PORT 0
tRLDV
A7-A0 FROM RI OR DPL
tAVWL tAVDV
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 16. External Data Memory Read Cycle
18
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52 IC80LV32
ALE
tWHLH
PSEN
tLLWL tWLWH tWHQX
A7-A0 FROM PCL INSTR IN
WR PORT 0
tAVLL tLLAX
A7-A0 FROM RI OR DPL
tQVWX
DATA OUT
tAVWL
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 17. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tQVXH tXHQX 0 tXHDV 1 2 tXHDX
VALID
DATAOUT DATAIN
3
4
5
6
7
SET TI
VALID
VALID
VALID
VALID
VALID
VALID
VALID SET RI
Figure 18. Shift Register Mode Timing Waveform
Integrated Circuit Solution Inc.
MC006-0B
19
IC80LV52 IC80LV32
tCLCX
Vcc -- 0.5V 0.45V
0.7Vcc 0.2Vcc -- 0.1
tCHCX
tCHCL tCLCL
tCLCH
Figure 19. External Clock Drive Waveform
P1.0-P1.7 P2.0-P2.3 PORT 0
tELQV
ADDRESS
tAVQV
DATA OUT
tEHQZ
P2.7
Figure 20. ROM Verification Waveforms
Vcc - 0.5V 0.45V
0.2Vcc + 0.9V 0.2Vcc - 0.1V
Figure 21. AC Test Point
Note: 1. AC inputs during testing are driven at VCC - 0.5V for logic "1" and 0.45V for logic "0". Timing measurements are made at VIH min for logic "1" and max for logic "0".
20
Integrated Circuit Solution Inc.
MC006-0B
IC80LV52 IC80LV32
ORDERING INFORMATION COMMERCIAL TEMPERATURE: 0C to +70C
Speed 24 MHz Order Part Number IC80LV52-24PL IC80LV52-24PQ IC80LV52-24W IC80LV32-24PL IC80LV32-24PQ IC80LV32-24W Package PLCC PQFP 600mil DIP PLCC PQFP 600mil DIP
24 MHz
Integrated Circuit Solution Inc.
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
Integrated Circuit Solution Inc.
MC006-0B
21
IC80LV52 IC80LV32
22
Integrated Circuit Solution Inc.
MC006-0B

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